Modern and cost effective design of electronic devices requires denser packaging of the electronic components on the printed circuit boards PCBs. Denser packaging also requires more effective current- and thermo-management design. In power electronics such as DC-DC converters, multilayer PCBs are often used where conductive layers (such as copper layers) embedded in the PCB carry high currents. These high currents require cooling of the interior of the PCB in addition to the cooling of the individual electronic components mounted on the exterior. The high currents also need to be transported between different copper layers which mean that some copper layers need to be galvanic interconnected.
There are several established methodologies according to standards and best practice techniques:                The use of high thermo conductive laminates to enhance the thermal transport.        Use of plated copper vias, through holes across the multi-layer structure for current transport. The vias could be unfilled or filled for example with solder.        Use of thermo conductive packages by the means of gap fillers, tapes, adhesives, chassis etc for thermal transport.        
High thereto conductive laminates are often unsuitable for electronics that require high potential isolation. Increased high potential isolation requires enhanced dielectric components (laminates, coatings, etc) which are in contradiction with the characteristics for high thereto conductive laminates.
Using vias for the transport of high currents have limitations. The thickness for the copper layers on a PCB can easily be available up to 0.175 mm but the thickness of the via plating is limited to 0.05 mm which limits the conductivity. Vies properly filled with solder increases current and thermal conductivity between the copper layers, but provide very limited cooling of the interior of the PCB. In addition, filling vies with solder is an unreliable method. Due to different factors there is always a risk that the vies are not properly filled during the soldering process. Thin via platings and partly filled vies limit the possibilities to conduct heat and high currents thru a multilayer structure in a PCB. Gap fillers, tapes and adhesives limit the mounting freedom in the final assembly e.g. lead-free surface mounting profiles and specific chassis add significant costs to the design.
The European patent application with the publication number 0 378 211 discloses a multilayer PCB with a component that has pins penetrating the conductive layers of the PCB. The inventive concept in EP 0 378 211 is mainly to transfer heat generated in the component to a conductive layer in the PCB but do also allow for the transfer of heat from a conductive layer to the pins of a low heat chip. This is however normally not desired as it can result in that the low heat component becomes overheated which degrades performance.